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originally posted by daniellew@Aug 25 2006, 10:08 AM

i'm working with the standard 256mb ddr2 sdram that came packaged with the altera cyclone ii board. in sopc builder, with the target board specified to the cyclone ii dsp board (ep2c35), the ddr2 sdram controller megacore function defaults to 256mb properly.

the sdram component is connected to the cpu instruction master and data master.

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To the best of my knowledge, the standard designs (shipped with the kit) only allow you to access 64MB of the 256MB DIMM. (what does SOPC Builder tell you, not the DDR Megawizard??) Did you modify the design and, if so, how did you get it to work? The last time I tried (circa Nios II 5.0/Quartus II 5.0), SOPC Builder (appropriately, as the processor and toolchain don&#39;t support it) would not allow me to increase the address span, that the instruction master sees, beyond the 256MB limit.

I&#39;m not saying I don&#39;t believe you, I&#39;m just stating that, in my experience, the state you&#39;re in is not possible to reach when using the tools correctly.

Cheers,

- slacker