Forum Discussion
ContributorCan't instantiate GPIO Lite Intel
Hello,
I have checked the reference that you mentioned in the Max 10 GPIO User's Guide and can not find any way that I am not in compliance with the Specifications of the Max 10 GPIO. This is also substantiated by the fact that the design WORKS if I use the GPIO LVDS Receive Buffers and do the DDR function in logic. It just DOESN'T WORK when I use the GPIO LVDS DDR Receive Buffers.
I am 100% sure that I have assigned the LVDS Device pins correctly and that the pins assigned to these LVDS Signals are actually LVDS Pin Pairs and are correct. If they were incorrect, why would they work in the one case, and not in the other case?????
I am sorry that this is such a difficult problem, but I have recently checked the design's timing and my discrete logic implementation, even though it appears to work in the actual hardware, is not meeting timing constraints. Hence, I need the GPIO DDR Buffers to compile so that I can improve the timing performance.
Thanks for your continuing support,
Bill
Regular ContributorHello Bill,
I understand your frustration. I believe you get this error because your design does not meet the specification of Max 10 GPIO. Please compare your design with Max 10 GPIO especially on IP requirement. You can refer to page 6 from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
Thank you,
Amin
ContributorHello,
I have checked the reference that you mentioned in the Max 10 GPIO User's Guide and can not find any way that I am not in compliance with the Specifications of the Max 10 GPIO. This is also substantiated by the fact that the design WORKS if I use the GPIO LVDS Receive Buffers and do the DDR function in logic. It just DOESN'T WORK when I use the GPIO LVDS DDR Receive Buffers.
I am 100% sure that I have assigned the LVDS Device pins correctly and that the pins assigned to these LVDS Signals are actually LVDS Pin Pairs and are correct. If they were incorrect, why would they work in the one case, and not in the other case?????
I am sorry that this is such a difficult problem, but I have recently checked the design's timing and my discrete logic implementation, even though it appears to work in the actual hardware, is not meeting timing constraints. Hence, I need the GPIO DDR Buffers to compile so that I can improve the timing performance.
Thanks for your continuing support,
Bill
- AminT_Intel
Hello Bill,
I understand your frustration. I will do my best to assist you.
There are many documents about DDR that you can find from this file: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/archives/ug-m10-gpio-15.1.pdf . Your design should be working if your design meet all the specifications of your device. May I know what error did you get regarding the error to compile DDR buffer?
Thank you,
Amin.
- WShep1
Yes you are right. The pins that I am using are on the bottom of the device and LVDS DDR Buffers are not supported on the bottom of the device. Since the layout for this board is already complete, I will have to live with using the LVDS Receivers and doing the DDR Function with logic.
Thanks for all of your assistance,
Bill
