Forum Discussion
ContributorCan't instantiate GPIO Lite Intel
Hello,
I have checked the reference that you mentioned in the Max 10 GPIO User's Guide and can not find any way that I am not in compliance with the Specifications of the Max 10 GPIO. This is also substantiated by the fact that the design WORKS if I use the GPIO LVDS Receive Buffers and do the DDR function in logic. It just DOESN'T WORK when I use the GPIO LVDS DDR Receive Buffers.
I am 100% sure that I have assigned the LVDS Device pins correctly and that the pins assigned to these LVDS Signals are actually LVDS Pin Pairs and are correct. If they were incorrect, why would they work in the one case, and not in the other case?????
I am sorry that this is such a difficult problem, but I have recently checked the design's timing and my discrete logic implementation, even though it appears to work in the actual hardware, is not meeting timing constraints. Hence, I need the GPIO DDR Buffers to compile so that I can improve the timing performance.
Thanks for your continuing support,
Bill
Regular ContributorHello,
Can you give us a sample with the same error so we can further investigate?
Thank you.
- AminT_Intel
Hello,
Have you resolve your problem? Please let me know. I will have to close this case in 3 days if there is no further response.
Thank you.
WShep1Thank you for your response and I am sorry for the late reply. I have attached an archived project that shows the problem. In the "ZTest8_sensor_top.sv" top level design file, I have two different LVDS front ends instantiated and selected by the "ifdef" switch, "USEGPIOLITEDDR" found on line 362. One front end which is instantiated when "USEGPIOLITEDDR" is defined uses the GPIO Lite DDR. The other LVDS front end uses GPIO LVDS receivers and does the DDR function in logic. The second instantiation compiles and works while the first on will not compile and gives the following 4 errors:
Error (15853): Input port I of I/O input buffer "wds_data_receive_lvds2:u203|altera_gpio_lite:wds_data_receive_lvds2_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|diff_input_buf.diff_input_buf_without_nsleep.ibuf" must be driven by a top-level pin
Error (15853): Input port I of I/O input buffer "wds_data_receive_lvds2:u202|altera_gpio_lite:wds_data_receive_lvds2_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|diff_input_buf.diff_input_buf_without_nsleep.ibuf" must be driven by a top-level pin
Error (15853): Input port I of I/O input buffer "wds_data_receive_lvds2:u201|altera_gpio_lite:wds_data_receive_lvds2_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|diff_input_buf.diff_input_buf_without_nsleep.ibuf" must be driven by a top-level pin
Error (15853): Input port I of I/O input buffer "wds_data_receive_lvds2:u200|altera_gpio_lite:wds_data_receive_lvds2_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|diff_input_buf.diff_input_buf_without_nsleep.ibuf" must be driven by a top-level pinI am using Quartus 20.1 Lite
Thanks in advance for your assistance with this problem.
- AminT_Intel
Hello,
I cannot see errors that you have mentioned in your sample design.
Can I know which device are you using for your design and it's OPN? Have you used Quartus Standard version and see if you still get the same error?
Thank you.
- WShep1
I am using a MAX10 device - 10M50DAF484C6GES. I don't have a current license for 20.1 Standard. Hence, I can try to compile the design with it.
Did you compile the design with the "USEGPIOLITEDDR" in both states? If "USEGPIOLITEDDR" is defined it will compile with the GPIO DDR LVDS Receiver instantiated and if "USEGPIOLITEDDR" is commented out it will compile with the same GPIO LVDS Receiver that is used in both conditions to receive the clock signal and the DDR function is accomplished using Verilog logic. "USEGPIOLITEDDR" is found on line 373 of the ZTest8_sensor_top.sv file.
Are you getting no errors with "USEGPIOLITEDDR" in both states?
If you are not seeing the error, then this would indicate that there is some configuration issue with my computer. Would you consider doing a remote debugging session where you dial into my computer so that you can see the error happen on my computer?
