ContributorCan't instantiate GPIO Lite Intel
Hi,
I am trying to instantiate a DDR LVDS data receiver generated from the IP Catalog for a Max 10 FPGA. i am using the GPIO Lite Intel FPGA IP. The module definition in my system verilog top level design file is as follows:
wds_data_receive_lvds u20
)
.inclock (slvs_clk),
.dout (slvs_2bit_4chan_data_0), // 2bit output
.pad_in (slvs_chan_in_pad[0])
);
The signal "slvs_chan_in_pad[0]" is assigned in the Pin Planner as the positive input to a real lvds buffer. It is part of a 4 bit lvds interface ( input wire [3:0] slvs_chan_in_pad ).
When I try to compile the design, I get the error " 171000 Can't fit design in device" with no explaination of what the problem is.
Can anyone help me learn how to properly assign the lvds input pins to this GPIO Lite Intel FPGA DDR LVDS Receiver IP?
Hello,
I have checked the reference that you mentioned in the Max 10 GPIO User's Guide and can not find any way that I am not in compliance with the Specifications of the Max 10 GPIO. This is also substantiated by the fact that the design WORKS if I use the GPIO LVDS Receive Buffers and do the DDR function in logic. It just DOESN'T WORK when I use the GPIO LVDS DDR Receive Buffers.
I am 100% sure that I have assigned the LVDS Device pins correctly and that the pins assigned to these LVDS Signals are actually LVDS Pin Pairs and are correct. If they were incorrect, why would they work in the one case, and not in the other case?????
I am sorry that this is such a difficult problem, but I have recently checked the design's timing and my discrete logic implementation, even though it appears to work in the actual hardware, is not meeting timing constraints. Hence, I need the GPIO DDR Buffers to compile so that I can improve the timing performance.
Thanks for your continuing support,
Bill
