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Honored Contributor
Honored ContributorCan Qsys implement two processor with sharing 2 ddr2 sdram?
the scheme is : on Stratix IV EP4SGX230 {Processor1 Processor 2} |/ _________ \| {ddr2SDRAM1 ddr2SDRAM2 } operations: 1,time1 ,Processor 1 ACESS SDRAM1...
Altera_ForumHonored Contributor
Honored ContributorThe Avalon bus arbiters will allow both cpu (and any other Avalon masters) to access the memory - so there is not physical problem.
Logically you need to setup the software address maps so that the two processors aren't trying to use the same part of the memory.
