Can Nios be synthesized by Synplify or Amplify

Modelsim is what we claim support for, but our Verilog and VHDL are industry standard, so you should be able to put the .v or .vhd files into any simulator and make it simulate. Otherwise, since Sopc Builder gies you the v or vhd you should be able to go to most other applications for whatever...

One thing I remember is that some applications have problems with long signal names. That would be a problem with Sopc Buidler generated files, they're long.