can I use higer clock frequency than 50Mhz?

If there isn't a second clock on the PCB itself. then you can just use a PLL (Phase lock loop) and create a different clock based off of it.

At home I have a 50MHz oscilator that I bring up to 100MHz for my 1S10. I'd give you the steps to bring it into the design but I don't have Quartus installed (OS redo).

In Quartus you would double click your block diagram to bring up the parts list and you go to the I/O section (I forget the exact name).

Select Alt_Pll (again that might not be the exact name), when you select it I would use the megawizard since there are a lot of parameters for that one. If your NIOS II project doesn't have a block diagram then you would do this in whatever diagram it appears in.

For what you are doing you probably don't need any locking signals or anything like that just a clock input, the clock output (called c0), and if you want 75MHz then you select a multiplication factor of 3 and a division factor of 2. i.e. (50Mhz) * 3/2 = 75Mhz

When you rebuild the NIOS II system select the correct frequency if it's not already done for you (because if you use clock dependent cores like the RS-232 Uart this will be very important, and it also probably helps with pipeline optimizations).

Like I said I am able to exceed 100Mhz in fmax on my little 1S10, you can probably reach 125Mhz in the 1S40 part if your design isn't too busy (logic/routing wise). You're divice has 8 Plls if I remember correctly so if you wanted to do the same elsewhere in your circuit you have room to grow.

If you need more help let me know (I should have quartus installed by then)

Good-luck