Cached pipes

Hi all

I know that there is some kind of problem with instruction caching in the NIOS processor. BUT now I pose this question to you all:::::

Altera found a bug in the M4K blocks of memory when reading or writing to it in some instances. Isn't this the problem that every one has when you setup this Cach in the processor???? They also have some fixes available and the problem seems to be fixed in the next version FPGA's.