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Altera_Forum's avatar
Altera_Forum
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7 years ago

cache not enable

Dear all, I have some questions about the U-boot. The hardware board is designed by myself. The SoC is 10AS016E4F27E3SG. I run the Bootloader on the board and print the following informati...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

I'm not sure not having the cache enable at such an early point in the boot process is really a problem. I think the real problem is the SDRAM calibration that failed. You can compile a new version of the preloader wich will give you more output on the calibration process and where it fails, by changing the RUNTIME_CAL_REPORT to 1 in uboot-socfpga/board/altera/socfpga/sdram/sequencer_defines.h and recompiling it.

Have a look at https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/external-memory/emi_ip.pdf sections 17.4 and 17.5 for more information on how to debug calibration failures.