Altera_Forum
Honored Contributor
19 years agoCache bypass
Hello all,
I'm developing an application with two or more Nios II processors. There is a scheduller that select a thread to execute on a specific cpu. Any thread can run on any cpu. However, there is no support to any cache coherency mechanisms in Nios II, and I can't disable explicitly the cache. To solve this problem, I thinking in use the bit-31 cache bypass provided in the Nios II/f core. So, I should set to one the most-significant bit (bit 31) of the resource address (that is used for more of one cpu). Is there any way to do this for all addresses? I changed the the address references in linker script file (generated.x for applications builded in Nios II-IDE): From: sdram_UNUSED : ORIGIN = 0x01000000, LENGTH = 32
sdram : ORIGIN = 0x01000020, LENGTH = 16777184
__alt_data_end = 0x01100020; (used for stack) To: sdram_UNUSED : ORIGIN = 0x81000000, LENGTH = 32
sdram : ORIGIN = 0x81000020, LENGTH = 16777184 (bit-31 set to one)
__alt_data_end = 0x81100020; All the references were changed in .elf... but the nios2-download tool dowloaded the .elf at non valid address, and the nios couldn't execute it. Do you know any way to do that? Any another idea is welcome!!! Thanks all. Regards, Maikon