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Altera_Forum
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14 years ago

Cache Behavior on NIOS-II

Hi everybody, I'm working on a project that needs me to fully understand how many cycles does d-cache/ i-cache needs to fetch the whole cache line. Assuming that the cache line size is 32b...
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Altera_Forum
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14 years ago

Dual port the on-chip memory as tightly coupled code/data memory and to the avalon bus for other masters.

Remember not to try to give the cpu's data port access to tightly coupled data memory - that will give errors since the two blocks end up at the same address.

If you are reading from external memory (eg SDRAM) it will take considerably longer.