Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Cache Behavior on NIOS-II

Hi everybody, I'm working on a project that needs me to fully understand how many cycles does d-cache/ i-cache needs to fetch the whole cache line. Assuming that the cache line size is 32b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The instruction cache uses critical word first line filling. So if an instruction at address 20 was to be fetched and is not already cached then you can expect the instruction master to perform the reads at the following addresses:

(first) (last)

20, 24, 28, 0, 4, 8, 12, 16

These are pipelined reads so as long as the slave/fabric doesn't stall you can expect the read data to return back-to-back after 'x' number of cycles.