C2H Timing

first - 10x !!!

but, who decides memory acces priority ? if my C2H function needs a register from the sdram, and another component needs access at the same time ?

In SOPC Builder you can assign "arbitration shares". So by default each master as an arbitration share of 1 which implements equal fairness arbitration. In C2H there are pragmas that you use to tell the compiler to automatically set the arbitration share, you can find that in the pragma section of the C2H user guide as well as the C2H optimization chapter in the embedded design handbook.

The arbitration makes sure that only one master accesses a slave port at a time by asserting waitrequest to all the other masters that are attempting to access the same slave port. There is no way to ensure that one master *always* wins over another unless you created a bridge component that acted as an arbiter. This is easy to implement but is often overkill when arbitration share can *almost* do the same thing.

SOPC Builder generates slave side arbitration so the masters in your system are not in competition for a bus but rather a slave. So if your C2H accelerator accesses SDRAM while another mastering component like Nios II accesses on-chip RAM then both can occur simultaneously. If you have a data hazard in your code between the processor and C2H accelerator then it is up to you to handle it in your code since the tools won't know what your intention is. I've used the Mutex component for sharing information back and forth with a C2H accelerator to avoid data hazards in the past but there are other ways you can do this.