C2H speedup vs clearing data cache

Unfortunately there is no rule of thumb since this will be dependent on the main memory(s), cache size, and cache line size.

How you handle this is very system specific like you mentioned. If Nios II doesn't need to access this data much then I would allocate the data in a non-cached region of your memory space or use a tightly coupled memory (dual port it with C2H accessing the other port). If Nios needs to get at this data a lot you might be better off letting the processor clear it (some of the zeros may remain cached when it goes to use them for calculations).

The same can be said if you were using a DMA peripheral as well (actually your example is a zero stuffing DMA).