You probably are not meeting timing due to the division by 100. Right now C2H uses lpm_divide for that and doesn't add much pipelining. I'm guessing your Fmax if targeting Cyclone III is probably around 16MHz. There are a few ways around this:
1) Maybe your algorithm can be changed to avoid the division
2) Try using these serial dividers:
http://www.altera.com/literature/hb/nios2/edh_c2h_optimization_design_files.zip 3) Make a divider component that you can write data into and read results back out and access it like a memory
.... there might be others, I haven't had enough coffee to think of them. As a heads up option# 2 will become blocking for around 33 clock cycles since you are performing a 32-bit division. You might find that you don't need a lot of accuracy and can break down this division into a bunch of shifts and adds/subtracts. I wrote down how you can do that somewhere but can't remember for the life of me where I put it but if you google for it I'm sure you find it. The algorithm works by breaking the division down into fractions that have powers of 2 in the denominator (which you can use >> to divide).