Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI'm not familiar with VHDL (I switched to verilog long ago and have never looked back :)). By the sounds of it the accelerated HDL happens to contain a previously declared module/name called "IO". Just in case there are old files being left behind one thing you could try is deleting all the generated HDL files and the /db directory for your project, and then regenerate to see if that will compile.
If that doesn't work then I would open the generated HDL file and search for "IO" in there to find out what is causing it to be used.