Building a NiosV BSP using Ashling Riscfree CMake flow fails to compile HAL in Intel code.

I am seeing the following error when building the BSP for NiosV. The build failure is in the Altera HAL under HAL/inc/io.h when trying to build the macro for the 32-bit IOWR as follows:

Line 125 writes:

/* Performs swio instruction. BASE and OFFSET are byte-aligned */
#define SWIO(BASE, OFFSET, DATA) do { \
unsigned int __tmpData = (DATA); \
asm volatile ( \
"sw %[DATAReg], 0(%[addrReg])\n\t" \
: \
: [addrReg] "r"(BASE), [imm] "i"(OFFSET), [DATAReg] "r"(__tmpData) \
: "memory" \
); \
} while (0)

But this results in build error:

/Projects/BSP/DGC241/HAL/inc/io.h:126:34: error: expected expression before 'do'
126 | #define SWIO(BASE, OFFSET, DATA) do { \
| ^~

It can be resolved by commenting out the SWIO macro.