Bug in SOPC?

use component editor:

you create a new component,

(interface description to an external component, not an IP),

you get new signals in your top schematic to connect your SRAM,

you have to connect your SRAM to work properly).

HDL Files : no hdl files

Signals Tab:

Name Interface Signal Type Width Direction

address avalon_tristate_slave_0 address 18 input

data avalon_tristate_slave_0 data 16 bidir

cs_n avalon_tristate_slave_0 chipselect_n 1 input

wr_n avalon_tristate_slave_0 write_n 1 input

rd_n avalon_tristate_slave_0 read_n 1 input

be_n avalon_tristate_slave_0 byteenable_n 2 input

clk avalon_tristate_slave_0 clk 1 input

Interfaces Tab:

Name: avalon_tristate_slave_0

Type: avalon_tristate_slave

Slave addressing: Memory (use dynamic bus sizing)

Minimum Arbitration Shares: 1

Can receive stderr/stdout: No

Avalon Tristate Slave Timing:

Setup: 1 , Read Wait: 1 , Write Wait: 1 , Hold: 1 , Units: cycles

Read Latency: 0

SW FIlesw : no files

Component Wizard:

Component name: SRAM_512KBx16

Component Version: 1.01

Conponent Group: Memory

After generation you will get new signals in the top cpu symbol:

cs_n_to_the_sram_512kbx16_0

maybe you get also

write_n_to_the_sram_512kbx16_0

read_n_to_the_sram_512kbx16_0

then connect

cs_n_to_the_sram_512kbx16_0 --> RAM: \CS

write_n_to_the_sram_512kbx16_0 --> RAM:\WE

read_n_to_the_sram_512kbx16_0 --> RAM:\OE

tristate_bridge_0_byteenablen[1] --> RAM:\BHE

tristate_bridge_0_byteenablen[0] --> RAM:\BLE

tristate_bridge_0_address[18..01] --> RAM: A[17..0] (two bytes)

tristate_bridge_0_data[15..0] --> RAM:D[15..0]

(you can share the write and read signals with the tristate_bridge_signals:

tri_state_bridge_0_writen and tri_state_bridge_0_readn,

by manually changing the ptf file (reinsert component in SOPC!)

or using additional logic in top schematic)