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Andrew099's avatar
Andrew099
Icon for New Contributor rankNew Contributor
2 years ago
Solved

BSP fails to build for FreeRTOS on a Nios V with UART

I have a Nios V on a Max 10 with a UART (RS-232 Serial Port) Intel FPGA IP (and also JTAG UART). When I opened up the BSP editor, I selected FreeRTOS and went with all the defaults and made a BSP. Ho...
Nios Cpu
  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    2 years ago

    In the "freertos/drivers/src/":


    • intel_lw_uart_init.c
      • line 228~:

    if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))

    {

    ALT_FLAG_POST (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_SET);

    }


    • intel_lw_uart_read.c
      • line 205~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_READ_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);


    • intel_lw_uart_write.c
      • line 192~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);



EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Andrew,


We apologize for any inconvenience. Given this, is it okay to proceed with the Altera HAL with your design? Or do you have other FPGA?


Andrew099's avatar
Andrew099
Icon for New Contributor rankNew Contributor
2 years ago

We're using external flash to do execute in place, and so it doesn't matter to us that the .elf file won't fit on the Max 10 itself. We're still planning on using the Max 10, and given our current design, we have to use FreeRTOS. We think we know what we need to do going forward. Thank you for your help.