bridge between Altera Bus and Wishbone Bus

Hi lmxue518,

> is there anybody who know how to do such a thing?

I developed a Wishbone-Avalon bridge to use with the OpenCores PCI bridge ...

It's pretty straight forward as the two buses are very similar.

> and I don't know how to develp a bridge between Altera Bus and Wishbone Bus

First, read (and understand) the Avalon and Wishbone bus specifications:

http://www.opencores.org/projects.cgi/web/...e/wbspec_b3.pdf (http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf)

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

If all you need is an Avalon master to Wishbone slave you should have little trouble. It really

boils down to how you want to map Wishbone ACK, ERR & RTY to the Avalon waitrequest.

Regards,

--Scott