Bootloader size

Isn't it possible to do what they write about in the post I linked to in my first post?

The plan is to have the bootloader in on board ram, and load the sw image to sdram. If you look at the post

http://www.niosforum.com/forum/index.php?s...t=0&#entry10330 (http://www.niosforum.com/forum/index.php?s...t=0&#entry10330)

they describe exactly what I want to do. They give the following sopc settings:

Reset address: on chip ram

Exception address: user application memory (sdram)

edit:

More awake now, so I'll express myself more clearly.

I want to put the bootloder in on board ram, and let it load my image from uart to sdram. The memory where my bootloader lies will never be reused. My bootloader would like you said, poll the uart for data, place it in sdram, and finally point to the start address of the application when done. The exception address will be in sdram. The reset address will be in onboard memory, so that if the fpga is booted, it will run the bootloader again.

And my problem is like stated above, that the size of my bootloader is too big. Almost all the code comes from my syslib, so I guess the question is how I reduce the size of this. Do I make a separate syslib for the application, that only "knows" about the uart and other things I may need?