Forum Discussion
Honored ContributorBooting HPS from FPGA
Hello,
has anyone managed to boot the whole u-boot image (Bootloader) from FPGA? If so, how did you do this? There are tutorials for booting the HPS from FPGA with U-Boot SPL. The tutorials use the FPGA On-Chip Memory for just the Preloader and they load the actual Bootloader from SD-card or QSPI Flash. We have custom board with just blank eMMC-memory, EPCQ256 and Cyclone V SoC-device. I guess that it's possible to load the bootloader also from FPGA, but I haven't found any information about this. We would like to boot the U-Boot from the FPGA and then write the actual OS-image to eMMC-memory using Ethernet. Thanks, Joonas12 Replies
Altera_ForumYou are right, I've not seen an example that does that - my guess is that the internal memory are probably too "precious" to be allocated for the whole bootloader. Technically though I don't see any limitation in doing so - except that you've to probably have to modify spl.c to point to the next offset that is located over the H2F bridge.
- Altera_Forum--- Quote Start --- You are right, I've not seen an example that does that - my guess is that the internal memory are probably too "precious" to be allocated for the whole bootloader. Technically though I don't see any limitation in doing so - except that you've to probably have to modify spl.c to point to the next offset that is located over the H2F bridge. --- Quote End --- The actual U-Boot's size is 1553 Kbytes, so that doesn't fit into our device's On-Chip memory. Would it be possible to add Ethernet support to the U-Boot SPL? Or to use the UEFI bootloader? Arria 10 seems to support the UEFI bootloader. Is there support also for Cyclone V?
- Altera_Forum
I don't think it is possible to add Ethernet to the SPL - reason being, the small code size is meant for the HPS on chip RAM (64KB). Arria 10 meanwhile has much larger OCRAM at 256KB.
Yes, A10 support UEFI but CV does not. The other bootloader that Altera provides for CV is the MPL. - Altera_Forum--- Quote Start --- I don't think it is possible to add Ethernet to the SPL - reason being, the small code size is meant for the HPS on chip RAM (64KB). Arria 10 meanwhile has much larger OCRAM at 256KB. Yes, A10 support UEFI but CV does not. The other bootloader that Altera provides for CV is the MPL. --- Quote End --- Okay, A10 seems to have much better options :cool: Would it be possible to place the u-boot binary in the EPCQ-flash and then using the boot copier load the u-boot binary into the DDR-memory? Is there support in EDS-tools for the boot copier? NIOS II SBT seems to have this nice feature.
- Altera_Forum
Ok, if I got you correctly: device powers up --> FPGA complete programming --> HPS loads SPL from on chip memory --> SPL sets up HPS clocks, and readies the HPS DDR --> bootcopier/SPL copies uboot into HPS DDR --> HPS executes from DDR :huh:
I don't really know, but (1) the HPS DDR needs to be set up by SPL before the FPGA (boot copier) can access them, so this can't be done immediately after FPGA completes programming and the F2S bridges are enabled (2) SPL probably is not able to control the EPCQ controller to read/write data. Either way, this is probably way beyond my expertise :) I suggest you try contacting Altera support for this. - Altera_Forum--- Quote Start --- Ok, if I got you correctly: device powers up --> FPGA complete programming --> HPS loads SPL from on chip memory --> SPL sets up HPS clocks, and readies the HPS DDR --> bootcopier/SPL copies uboot into HPS DDR --> HPS executes from DDR :huh: I don't really know, but (1) the HPS DDR needs to be set up by SPL before the FPGA (boot copier) can access them, so this can't be done immediately after FPGA completes programming and the F2S bridges are enabled (2) SPL probably is not able to control the EPCQ controller to read/write data. Either way, this is probably way beyond my expertise :) I suggest you try contacting Altera support for this. --- Quote End --- Yes, this is getting quite tricky :D I found the AN736 (https://www.altera.com/en_us/pdfs/literature/an/an736.pdf), which describes how to use the Altera Serial Flash Controller with NIOS II. I could place NIOS II Processor on the FPGA to do the boot copier stuff. This way the uboot binary could be copied from EPCQ into HPS DDR. Ofcourse the NIOS2 must be held in reset until the HPS DDR is set up by the SPL.
- Altera_Forum
Hello,
I finally managed to boot the whole U-boot from FPGA. I wrote a small custom IP-block which copies the U-boot binary from EPCQ to HPS DDR. Preloader code must be also modified to stall the boot process till the boot copying is done. - Altera_Forum--- Quote Start --- Hello, I finally managed to boot the whole U-boot from FPGA. I wrote a small custom IP-block which copies the U-boot binary from EPCQ to HPS DDR. Preloader code must be also modified to stall the boot process till the boot copying is done. --- Quote End --- Great news :) I understand that the code might be proprietary - perhaps you can list down some guidelines to those who would like to attempt the same thing in the future?
- Altera_Forum
Here are the guidelines to boot u-boot with EPCQ-memory:
1. The EPCQ-memory must be programmed with JIC-file that includes the U-boot binary at 0x100040 and FPGA image (includes the Preloader and possible IP for boot copying). 2. The U-boot binary must be transferred from EPCQ-memory to HPS-DDR (to memory address CONFIG_SYS_TEXT_BASE, defined in socfgpa_common.h). This can be implemented in FPGA with custom IP or in Preloader code using memcpy(). 3. The preloader code must modified to stall the boot process during the U-boot binary copying (/arch/arm/cpu/armv7/socfpga/spl.c). I implemeted this with simple memory polling. The custom IP writes "boot copy completed"-code to predefined memory address. The preloader polls this memory address until the "boot copy completed"-code is found. - Altera_Forum
Thanks for your sharing :)
- AKb
Occasional Contributor
Hello,
I have a custom board with cyclone V SOC . I have a 1Gbit QSPI flash attached to the HPS portion of SOC. I want to boot the HPS with qspi flash. I able to do it debug mode. But not able to do it in program mode. what i mean is that i am able to load the rbf files into the qspi flash and read back this files and program the fpga successfully in debug mode. But when i try to do it program mode it is not working. I have generated preloader_-mkpimage.bin file with all the necesssary settings as mentioned in HPS qspi boot guide documentation. i load this preloader-mkpimage in 0x00000000 address of QSPI flash using the commands in SOC Command shell. then i load my application bin file generated after compilation of my design at 0x60000 address of flash by using commands in SOC EDS Command shell. Both this operation is successfull. MSEL pins are correctly selected for QSPI Boot. When i reboot the equipment the system is not booting. Am i missing certain settings at bsp generation or in make file or the linker file. Please specify.
Regards
Avi
