Booting HPS from FPGA

Ok, if I got you correctly: device powers up --> FPGA complete programming --> HPS loads SPL from on chip memory --> SPL sets up HPS clocks, and readies the HPS DDR --> bootcopier/SPL copies uboot into HPS DDR --> HPS executes from DDR :huh:

I don't really know, but (1) the HPS DDR needs to be set up by SPL before the FPGA (boot copier) can access them, so this can't be done immediately after FPGA completes programming and the F2S bridges are enabled (2) SPL probably is not able to control the EPCQ controller to read/write data.

Either way, this is probably way beyond my expertise :) I suggest you try contacting Altera support for this.