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Ok, if I got you correctly: device powers up --> FPGA complete programming --> HPS loads SPL from on chip memory --> SPL sets up HPS clocks, and readies the HPS DDR --> bootcopier/SPL copies uboot into HPS DDR --> HPS executes from DDR :huh:
I don't really know, but (1) the HPS DDR needs to be set up by SPL before the FPGA (boot copier) can access them, so this can't be done immediately after FPGA completes programming and the F2S bridges are enabled (2) SPL probably is not able to control the EPCQ controller to read/write data.
Either way, this is probably way beyond my expertise :) I suggest you try contacting Altera support for this.
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Yes, this is getting quite tricky :D I found the AN736 (
https://www.altera.com/en_us/pdfs/literature/an/an736.pdf), which describes how to use the Altera Serial Flash Controller with NIOS II. I could place NIOS II Processor on the FPGA to do the boot copier stuff. This way the uboot binary could be copied from EPCQ into HPS DDR. Ofcourse the NIOS2 must be held in reset until the HPS DDR is set up by the SPL.
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