Forum Discussion
Occasional ContributorBooting from offboard CFI directly connected to FPGA
Hi,
both AS and PP configuration interface are using dedicated FPGA pins and can't be replicated on other pins. That's because the specific function is built-in to the FPGA, working before any user code has been loaded. NIOS boot is controlled by HDL code and can basically use any memory interface.
While AS configuration is performed autonomously by FPGA, PP needs an external controller, usually MAX V CPLD. Configuration data is presented to FPP data lines (either 16 or 32, depending on the mode) and clocked in by DCLK.
Occasional ContributorFvM,
Thank you for your response. If I am understanding you correctly, even though we are replicating the CFI and QSPI interface over FMC, there is no way to configure the Cyclone 10 using this interface?
For example could we not use the the Generic Serial Flash Interface IP to define a new configuration interface over the FMC connector?
Additionally, for configuring the Cyclone 10 using CFI wouldn't we need to use a passive scheme? From my research, passive configuration schemes seem to require a CPLD or in the case of the Cyclone 10 GX dev kit, a Max 10. Is this correct?
Thank you
Super ContributorHi,
both AS and PP configuration interface are using dedicated FPGA pins and can't be replicated on other pins. That's because the specific function is built-in to the FPGA, working before any user code has been loaded. NIOS boot is controlled by HDL code and can basically use any memory interface.
While AS configuration is performed autonomously by FPGA, PP needs an external controller, usually MAX V CPLD. Configuration data is presented to FPP data lines (either 16 or 32, depending on the mode) and clocked in by DCLK.
