Forum Discussion
Occasional ContributorBooting from offboard CFI directly connected to FPGA
Hi,
both AS and PP configuration interface are using dedicated FPGA pins and can't be replicated on other pins. That's because the specific function is built-in to the FPGA, working before any user code has been loaded. NIOS boot is controlled by HDL code and can basically use any memory interface.
While AS configuration is performed autonomously by FPGA, PP needs an external controller, usually MAX V CPLD. Configuration data is presented to FPP data lines (either 16 or 32, depending on the mode) and clocked in by DCLK.
Occasional ContributorIf there is any information that I unintentionally left out or there is more context that I could provide, please let me know. I am still working on finding a solution to this.
To be clear I have a Cyclone GX 10 dev kit which is connected to a proprietary board using the FMC connector. On this board is a QSPI chip and a CFI chip. I am trying to configure the Cyclone 10 FPGA and boot a NIOS from either of these chips.
From everything I have been reading, it is uncommon for the memory devices to be connected to the Cyclone 10 FPGA but not the Max 10 or a CPLD which orchestrates the configuration process.
Hypothesis 1.) FPGA configuration is not possible without the offboard memory being connected to the Max 10.
Hypothesis 2.) Booting NIOS from offboard memory should be possible given correct memory vectors and tristate controller / bridge.
If anyone has any thoughts on this, it would be very helpful. As I said, I am new to FPGAs and the only evidence I have to support my hypothesis is that I cannot find any examples where the FPGA is configured from memory that is not connected to a CPLD or Max 10 device. Likewise, I have not seen the NIOS booted from memory which is not connected to a CPLD or Max 10 but intuitively believe it would be possible based on the capabilities stated in the "Booting from CFI" tutorial in the main post.
