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Altera_Forum
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13 years ago

boot NIOS from EPCS flash and use SDRAM to store instructions and data

Hi! In the qsys I have: 1. Clock Source 2. On-Chip Memory 3. Nios II Processor 4. System ID 5. JTAG UART 6. EPCS Serial Flash Controller 7. PIO 8. SDRAM Controller I want to use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

*.hex file exist in "synthesis" folder. The first EPCS connected to a FPGA configuration pins. The second EPCS device connected to the regular I/O pins, EPCS flash Controller in Qsys assigned to this pins. Reset vector is set to this EPCS Controller. Is this configuration correct?