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Honored Contributor
Honored ContributorBasic SDRAM/NIOS question
Hello: I'm new here. Here's a fairly basic question (I think)... an answer to which I have been unable to find. I have a NIOS2 cyclone development board. What I want to do is r...
Altera_ForumHonored Contributor
Honored ContributorSounds like you need to buffer this data (using a FIFO). So contents are read out at 5MHz, and data is written into it at something considerably higher. Using signals that tell you whether the buffer is full (or close to getting full) you can have the master back off from writing into it. This is common practice in DSP type applications where you have to keep data rates constant.
