Honored Contributor
Honored ContributorIt seems that the problem was the interdependency between consecutive instructions affecting the MPU registers. I started noting that when running the program step by step everything runs ok, while when running freely the read value from the mpubase was incorrect. I discovered that changing instruction order so that some other instructions are executed between consecutive accesses to the mpu registers corrected the error.
So, to be on the safe side I added a "flushp" instruction after each write transfer to mpubase or mpuacc in order to flush the instruction pipeline. The odd thing is that the same problem was affecting the write region operations provoking erratic behavior. The documentation (Nios II Processor Reference Handbook) states that wrctl to mpubase and mpuacc do not flush the pipeline, and so system software is "responsible for flushing the pipeline as needed", but more emphasis on the fact that it is needed between the different transfers necessary to complete a single read region or write region operation would be welcome.
