Avalon Speed

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originally posted by fplank@Sep 18 2006, 09:31 AM

hello

can anybody give me a iead how fast a avalon bus works.

i designed a hardwar which gets data from the software via the avalon bus. i write via the iowr on the bus. this is a very time critical part.

so my question how fast is a write on the avalon bus about. i can i achiev a higher speed.

thanks

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Assuming no other masters are attempting to access your designation (and no wait states either) then the numbers shown in here should tell you how fast your writes are:

http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf (http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf)

By the way, can you use a DMA in your system? If so then you may achieve better efficiency using it. With a DMA, a destination memory that has a write latency = 0, and no other masters accessing the destination you should be able to achieve a write every clock cycle assuming no wait states occur. I recommend taking a look at this document to learn more about how the switch fabric works:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

Hello

Thanks first for your help. But i&#39;m pritty new in this development area, so i have some problems with your answer.

Fact is that i read some data from the avalon bus, do some small calcolations, and write on the avalon bus. This time needs more than 8ms. I can not believe this bad performance.

So what can be this delay. Or is this a regular delay?

I have a Nios /f 85Mhz. Connected my Hw with the Slave port of the NIOS would the Master be better? My Hw is running on 50Mhz.

Do i have a problem with the JTAG. I have the same speed with printf() and without. Sould a printf which is written via the JTAG to the terminal not i high delay?

I hope you can help me

sorry for my english

cu flo

Hello

Again...

Perhaps you can tell me whats the fastest way to send the Nios from a HW 32bits and receive again 32 bits. In between there are some small calculations.

thanks again

flo

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originally posted by fplank@Sep 19 2006, 02:14 AM

hello

again...

perhaps you can tell me whats the fastest way to send the nios from a hw 32bits and receive again 32 bits. in between there are some small calculations.

thanks again

flo

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Hi,

From my pass experience using Nios (not Nios II) which communicate to a user peripheral, using fixed-wait-state = 1 clock cycle. Writing to or reading from a avalon interface register (32-bit) takes more than 10 clock cycles to complete.

Even we need only a line of C code for that data transfer (either write or read 32-bit), the GNU compiler generates few lines of assembly code (around 5-6 lines), this is why it takes more than 10 clock cycles. That few lines of assembly code is essential for Nios processor to initiate its window registers for the data transfer. Such condition is just like when we invoke a function, it actually involves pushing parameters on stack, adjust the stack pointer, adjust the base pointer, store the return address, etc.

In my work, I write 4 sets of 32-bit data, I thought it would takes only 4 or 8 clock cycles, but it turns out to be 42 clock cycles (10 times more than the expectation). If I encapsule the 4 write operations in a function, then invoke that function and pass in 2 parameters, then the 4 write operations are executed, and return; it takes me about 90 clock cycles.

I don&#39;t think using DMA would help if your program execution is highly sequential, and you only need a few times of data transfer through Avalon Bus.

Hope this would help. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

This is Nios II processing time that you are running into and not Avalon. I recommend taking a look at your system implementation to see if it merits hardware acceleration (co-processing, DMA, etc...) Like suntick said if you have highly sequential code then you may not see a lot of gains using hardware acceleration. This is not always the case since sequential algorithms can sometimes be pipelined in hardware in such a way that back to back data can be processed (it&#39;s algorithm dependent).

I think if you describe your data flow a bit more and the nature of your alogrithm you may get more precise answers on how to improve your processing latency.