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Altera_Forum
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19 years ago

Avalon slave write cycle to 16-bit SRAM

Hello,

I am trying to interface Nios2 processor running at 80MHz clock to an external SRAM chip using tristate bridge. External SRAM is a single 512kX16-bit chip, fast 8ns grade.

I was hoping to get single cpu cycle read/write but it seems it is not doable.

CPU is doing two 16-bit cycles to write 32-bit value in SRAM and it holds the /CS and /WE signals low for the two write cycles changing only the address. Of course SRAM does only the second, since from its point of view the write cycle ends only when /CE or /WE goes up.

The only way I see to solve this problem is to add one hold-time cycle to this SRAM interface. This way the /WE signal will be set to high after the first 16-bit write and the SRAM will see two separate write cycles. But, it will mean that each write of 16-bit value would require 2 cycles, it makes write cycles twice slower.

Is there any other way to solve this problem using one 16-bits wide SRAM chip ?

Przemek.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I think (have not tested it) that Avalon decomposes each 32 access into two 16bit cycles.

    If you would like to create a faster optimized 32bit access, you will have to write a 32bit HDL component that will accept 32bit cycles from avalon and create two fast cycles on the SRAM interface. But that way you will have to implement 16bit and 8bit access too.

    It is probably easier to only modify the avalon timing parameters (setup, wait, hold).

    Than you may speed up the processor to 100MHz (throw away some unused SOPC peripherals). Or place only the SRAM on a faster clock, but this will create clock domain crossing, which will probably slow down your system instead of speeding it up.

    IzI