Avalon slave write cycle to 16-bit SRAM

I think (have not tested it) that Avalon decomposes each 32 access into two 16bit cycles.

If you would like to create a faster optimized 32bit access, you will have to write a 32bit HDL component that will accept 32bit cycles from avalon and create two fast cycles on the SRAM interface. But that way you will have to implement 16bit and 8bit access too.

It is probably easier to only modify the avalon timing parameters (setup, wait, hold).

Than you may speed up the processor to 100MHz (throw away some unused SOPC peripherals). Or place only the SRAM on a faster clock, but this will create clock domain crossing, which will probably slow down your system instead of speeding it up.

IzI