Avalon OpenCores MAC 10/100 + µClinux

<div class='quotetop'>QUOTE (ppitou @ Jul 1 2009, 12:04 PM) <{post_snapback}> (index.php?act=findpost&pid=22982)</div>

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papyenfurie

1) in sopc builder, I believe the igor_mac should be connected to the SRAM or the SDRAM

2) you are missing connections to the etxd[7..0] from the cpu symbol

3)I hope the MDIO symbol you have has an iobuf in there[/b]

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@ ppitou :

thanks you so much for your useful remarks it works perfectly now :rolleyes:

here are some screenshots of the modifications :

1) connecting tx_master and rx_master (igor_mac) to avalon memory mapped slave (SDRAM controller) + connecting control_port (igor_mac) to data_master (nios_cpu)

http://img6.imageshack.us/img6/7224/sdramigormac.jpg (http://img6.imageshack.us/img6/7224/sdramigormac.jpg)

2-3) add "etxd[3..0]" on the output wire + replace the MDIO module (Verilog) with a tristate buffer "tri" from Quartus lib

http://img33.imageshack.us/img33/6571/tristateetxd30.jpg (http://img33.imageshack.us/img33/6571/tristateetxd30.jpg)

Hope it could help someone one day ;)