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Honored ContributorAvalon MM slave template problem
Hi all,
I am using SOPC to build a Nios II system and also using Avalon MM slave template. Below is the code of my top level module:module userc
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch
//////////////////////// LED ////////////////////////
LEDR, // LED Red
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE // SDRAM Clock Enable
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_24; // 24 MHz
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// DPDT Switch ////////////////////////
input SW; // Toggle Switch
//////////////////////////// LED ////////////////////////////
output LEDR; // LED Red
/////////////////////// SDRAM Interface ////////////////////////
inout DRAM_DQ; // SDRAM Data bus 16 Bits
output DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
wire CPU_CLK;
wire CPU_RESET0;
wire CPU_RESET1;
wire CPU_RESET2;
wire CPU_RESET3;
wire CPU_RESET4;
wire CPU_RESET5;
wire CPU_RESET6;
wire CPU_RESET7;
wire CPU_RESET8;
wire CPU_RESET9;
wire CPU_RESET10;
wire CPU_RESET11;
wire CPU_RESET12;
wire CPU_RESET13;
wire CPU_RESET14;
wire CPU_RESET15;
wire CPU_RESET161;
wire CPU_RESET162;
wire CPU_RESET163;
wire CPU_RESET164;
wire CPU_RESET165;
wire CPU_RESET166;
wire CPU_RESET167;
wire CPU_RESET168;
wire CPU_RESET169;
wire CPU_RESET1610;
wire CPU_RESET1611;
wire CPU_RESET1612;
//assign FL_RST_N = 1'b1;
//assign CPU_RESET161 = 16'b0;
//assign CPU_RESET162 = 16'b0;
//assign CPU_RESET163 = 16'b0;
//assign CPU_RESET164 = 16'b0;
//assign CPU_RESET165 = 16'b0;
//assign CPU_RESET166 = 16'b0;
//assign CPU_RESET167 = 16'b0;
//assign CPU_RESET168 = 16'b0;
//assign CPU_RESET169 = 16'b0;
//assign CPU_RESET1610 = 16'b0;
//assign CPU_RESET1611 = 16'b0;
//assign CPU_RESET1612 = 16'b0;
//Reset_Delay delay1 (.iRST(1'b1),.iCLK(CLOCK_50),.oRESET(CPU_RESET));
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK));
system_0 u0 (
// 1) global signals:
.clk(CPU_CLK),
.reset_n(1'b1),
// the_LEDR
.out_port_from_the_LEDR(LEDR),
// the_Switch
.in_port_to_the_Switch(SW),
// the_sdram_0
.zs_addr_from_the_sdram_0(DRAM_ADDR),
.zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram_0(DRAM_CAS_N),
.zs_cke_from_the_sdram_0(DRAM_CKE),
.zs_cs_n_from_the_sdram_0(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram_0(DRAM_DQ),
.zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram_0(DRAM_RAS_N),
.zs_we_n_from_the_sdram_0(DRAM_WE_N),
// the_slave_template_0
.user_datain_0_to_the_slave_template_0(CPU_RESET1612),
.user_datain_10_to_the_slave_template_0(CPU_RESET1610),
.user_datain_11_to_the_slave_template_0(CPU_RESET1611),
.user_datain_12_to_the_slave_template_0(CPU_RESET12),
.user_datain_13_to_the_slave_template_0(CPU_RESET13),
.user_datain_14_to_the_slave_template_0(CPU_RESET14),
.user_datain_15_to_the_slave_template_0(CPU_RESET15),
.user_datain_1_to_the_slave_template_0(CPU_RESET161),
.user_datain_2_to_the_slave_template_0(CPU_RESET162),
.user_datain_3_to_the_slave_template_0(CPU_RESET163),
.user_datain_4_to_the_slave_template_0(CPU_RESET164),
.user_datain_5_to_the_slave_template_0(CPU_RESET165),
.user_datain_6_to_the_slave_template_0(CPU_RESET166),
.user_datain_7_to_the_slave_template_0(CPU_RESET167),
.user_datain_8_to_the_slave_template_0(CPU_RESET168),
.user_datain_9_to_the_slave_template_0(CPU_RESET169),
.user_dataout_0_from_the_slave_template_0(CPU_RESET0),
.user_dataout_10_from_the_slave_template_0(CPU_RESET10),
.user_dataout_11_from_the_slave_template_0(CPU_RESET11),
.user_dataout_12_from_the_slave_template_0(CPU_RESET161),
.user_dataout_13_from_the_slave_template_0(CPU_RESET162),
.user_dataout_14_from_the_slave_template_0(CPU_RESET163),
.user_dataout_15_from_the_slave_template_0(CPU_RESET164),
.user_dataout_1_from_the_slave_template_0(CPU_RESET1),
.user_dataout_2_from_the_slave_template_0(CPU_RESET2),
.user_dataout_3_from_the_slave_template_0(CPU_RESET3),
.user_dataout_4_from_the_slave_template_0(CPU_RESET4),
.user_dataout_5_from_the_slave_template_0(CPU_RESET5),
.user_dataout_6_from_the_slave_template_0(CPU_RESET6),
.user_dataout_7_from_the_slave_template_0(CPU_RESET7),
.user_dataout_8_from_the_slave_template_0(CPU_RESET8),
.user_dataout_9_from_the_slave_template_0(CPU_RESET9)
);
fuz fuz1 (
.clk(CPU_CLK),
.in0(CPU_RESET0),
.in1(CPU_RESET1),
.in2(CPU_RESET2),
.in3(CPU_RESET3),
.in4(CPU_RESET4),
.in5(CPU_RESET5),
.in6(CPU_RESET6),
.in7(CPU_RESET7),
.in8(CPU_RESET8),
.in9(CPU_RESET9),
.in10(CPU_RESET10),
.in11(CPU_RESET11),
.outa(CPU_RESET12),
.outb(CPU_RESET13),
.outc(CPU_RESET14),
.outd(CPU_RESET15)
);
endmoduleIOWR_8DIRECT(SLAVE_TEMPLATE_0_BASE,offset,data)1 Reply
Altera_ForumThe only time you can read back what you wrote is when you setup the component for software loopback (or whatever it's called) in the GUI. It looks like to me you have separate inputs and outputs and your inputs are grounded in your HDL file.
