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Altera_Forum
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12 years ago

Avalon-MM-Slave address alignment

Hi All I have aquestion regarding the address alignment of a an-MM slave. My MM-Save has an avs_readdata and avs_writedata port each 512 bit wide. Now I'm trying to write the custom prip...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

thanks for your answer!

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But it won't generate bursts longer than a cache line.

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The cache line is defined as 32, but the Nios refuses to make bursts longer than 8. I'd be perfectly fine with a 32-wide burst. This applies to both read and write bursts. :(