Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Avalon-MM-Slave address alignment

Hi All I have aquestion regarding the address alignment of a an-MM slave. My MM-Save has an avs_readdata and avs_writedata port each 512 bit wide. Now I'm trying to write the custom prip...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

thanks for your answer!

--- Quote Start ---

But it won't generate bursts longer than a cache line.

.

--- Quote End ---

The cache line is defined as 32, but the Nios refuses to make bursts longer than 8. I'd be perfectly fine with a 32-wide burst. This applies to both read and write bursts. :(