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Altera_Forum
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19 years ago

Avalon Master/Slave Interface Problem

I have created an Avalon Master Writer and an Avalon Slave Writer in Verilog. I believe I am properly adhering to the timing diagrams described in the Avalon Bus Specification for both modules. Bot...
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Altera_Forum
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19 years ago

The issue was that my Avalon Master module was set to "Big Endian" when I configured my system in SOPC builder. The Slave module, by default, is configured to be "Little Endian". Therefore, the data that I was passing from Master to Slave was flip-flopped, this was the source of my problem.

After reading the Avalon spec, it was my understanding that even if one module was Big Endian and another was Little Endian, that Avalon would take care of the Endianness and make sure that data was transferred accordingly. This assumption, however, was incorrect.

Please beware of this.