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Honored Contributor
Honored ContributorAvalon Master write does not write
My sopc modul has 3 Interfaces. avs_slavereg that holds the registers the nios reads from and writes to to control this modul avm_readmaster a read only a master that reads data from sdram...
Altera_ForumHonored Contributor
Honored Contributorwe enabled for both master the access to offchip 8but sram.
if we write to sram, the writes are executed and offchip sram holds the data :-) if we write to sdram, nearly no write is executed :-( same master, same source, same compilation, only different target. in both cases write is asserted. for ext. sram we see waitrequests for sdram we never see waitrequests. Michael Schmitt
