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Honored Contributor
Honored Contributoravalon master mode problem
I use the avalon master mode to transfer data from fpga fifo to sdram. To debug this design, i use two fifo, the content is same betwen the two fifo. The fifo mode is show-ahead, The two ...
Altera_ForumHonored Contributor
Honored ContributorI change my HDL code.
I add an wait state when i finish write two data. And this time, the result is right, I believe there is a bug in SDRAM controller. When i want to write three data, the third data is wrong.
