Altera_Forum
Honored Contributor
Honored Contributoravalon master mode problem
I use the avalon master mode to transfer data
from fpga fifo to sdram. To debug this design, i use two fifo, the content is same betwen the two fifo. The fifo mode is show-ahead, The two fifo is rxfifo and debugfifo. The data in debug fifo is(i only list 30 data) temp is 420 temp is 1014 temp is 2017 temp is 301b temp is 4020 temp is 5fde temp is 6000 temp is 7000 temp is 8000 temp is 9014 temp is a000 temp is b000 temp is c000 temp is d000 temp is e000 but when i printf the sdram data(It should be same with the the fifo data if temp is 420 temp is 1014 temp is 4b69d587 ----------------------- temp is 301b temp is 4020 temp is 5fde temp is 6000 temp is 7000 temp is 8000 temp is 9014 temp is a000 temp is b000 temp is c000 temp is d000 temp is e000 data 3 is wrong. ????? Why?? do you encounter the same problem??? I think this is the sdram controller problem . the following is my hdl code assign sdram_interface_writedata = rxfifo_dataout_reg ; always@(posedge clk or negedge rst_n) begin if(!rst_n) rxfifo_dataout_reg <= 32'b0; else rxfifo_dataout_reg <= rxfifo_dataout; end always@(master_active or sdram_interface_waitrequest) begin if(master_active) begin if(!sdram_interface_waitrequest) rxfifo_rdreq = 1'b1; else rxfifo_rdreq = 1'b0; end else begin rxfifo_rdreq = 1'b0; end end always@(posedge clk or negedge rst_n) begin if(!rst_n) begin sdram_interface_address[23:0] <= 24'b0; sdram_interface_write_n <= 1'b1; sdram_interface_read_n <= 1'b1; sdram_interface_address[24] <= 1'b1; counter <= 22'b0; end else begin if(master_active) begin sdram_interface_write_n <= 1'b0; sdram_interface_address[24] <= 1'b1; if(!sdram_interface_waitrequest) begin sdram_interface_address[23:0] <= {counter,2'b0}; counter <= counter + 1'b1; end else begin sdram_interface_address[23:0] <= {counter,2'b0}; counter <= counter; end end else begin sdram_interface_write_n <= 1'b1; sdram_interface_address <= 25'b0; end end end rx_fifo rx_fifo_inst(.data({frame_buffer_address[19:0],frame_buffer_dataout}),.wrreq(fra me_buffer_write),.rdreq(rxfifo_rdreq), .clock(clk),.q(rxfifo_dataout),.empty(rxfifo_empty)); debug_fifo debug_fifo_inst(.data({frame_buffer_address[19:0],frame_buffer_dataout}),.wrreq( frame_buffer_write),.rdreq(debugfifo_rdreq), .clock(clk),.q(debugfifo_dataout));
