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Altera_Forum
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13 years ago

Avalon bus with 2 Avalon_MM_ Slaves fails to work (works fine with 1...)

Hi All, I have designed an Avalon bus with 1 Master and 1 Slave, it works greate. I can do write and read just fine. OK, so I added another Master and another Slave, the first Slave at b...
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Altera_Forum
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13 years ago

Yes, of course I simulated the dual Slaves with two sets of user signals including the chipselect signal. In all cases only the lower addresses Slave responded with with a chipselect. The purpose of a chipselect is to qualify the Write and Read signals. The statement you are quoting is contradictory in nature, isn't it?

If you have 2 instances of the Slave mapped to diferent address ranges I would expect all associated control signals and in particular the chipselect to respond ONLY to accesses made in these addresses.

There is deffinitly a bug here ! Or else, you have to use only 1 Slave and qualify all its signals with external address decodes if you want to use several Slaves.

Thanks,

Shvitzer