Honored ContributorFolks,
Came across an interesting problem in my custom peripheral logic and was wondering what the Avalon bus Address bus state is between bus cycles? The book shows a black bar signifying "undefined" (?). What does it actully do? I wrote an avalon bus simulator to test my peripherals and would like to know what this really is. If you use 0, you could get glitchy results.
Honored ContributorEdward,
I think that since the address is a registered output, it will hold the previous value until a new value is written out. -- TerryHonored ContributorActually address can, and does, jump around quite a bit. It is registered, but not registered "just for the view of the slave" (if that makes any sense). The general idea is to reduce muxing (which eats LEs and slows F-max) as much as you can... in the simple case of a single master and many slaves, you will probably see the address to all slaves indicative of what the master is doing.
If I remeber correctly read, write, and chipselect are the only qualified signals delivered to the slave. The Avalon spec can confirm this.
