Avalon Bridges

Hi Longshot,

i just read the doc about this avalon to avalon bridge. Maybe your bridge could help me to gain the performance and resources used.

The project(s) i am currently working on has a couple of avalon masters.

The target FPGA is an EP2C50F484I8N and fniosclock is 64MHz. Sometime it is hard to keep the 64MHz.

The seven avalon masters are :

niosII-F

ethernet Mac 100MBit

4x self written interfacemaster 32-Bit with up to 1,6MByte/sec

adc streaming master 32-Bit with 4MByte/sec

and a couple of slaves (uart,timer,epcs,jtag,spi,1wire,tristate cfi ...)

all masters read and write only to the sdram. except the nios that also read and writes to all other slaves.

my first idea is to use a registered bridge and put all slaves only the nios comunicates with into. but then i need access to all 32 ints. i guess this could seperate the load and speed up fmax.

is there a chance with one of these bridges to speed up nios & sdram without incrementing the clock of all the other masters ?

should i add a (a)sync. fifo bridge to let the nios / sdram run at a higher clock rate (as high as possible) ?

would any bridge be usefull to be put into the master connections ?

if you need more information like the ptf let me know. i would greatly try your bridges if this project yould benefit from it.

Thanks in advance.

Michael Schmitt

PS: I use nearly all 32 IRQs ...