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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria 10 with separate hardened DDR controller for PL and HPS

I have come up with a set of requirements for the memory and I realized my PL memory needs are critical. I understand there is a x72 DDR4 hardened PHY+Controller+MPFE in the Arria10 and I'd like t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Is there linux support to access FPGA DDR?

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Are you saying you would like to use HPS to access the FPGA DDR memory over the H2F bridge? Right now I don't think the HPS can support 2 memory controller instances (one in its own HPS DDR and the other FPGA memory) - besides, it would be quite inefficient to do it over the H2F bridge. I believe letting the FPGA access the HPS DDR over the F2S bridge is a better alternative.