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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria 10 SPI Master bits per word support

Hi All,

We are using Arria 10 SOC FPGA and interfacing SPI slave device which needs 20-bit stream of data as input.

Here we have few questions on Arria 10 SPI controller.

1. What is the minimum and maximum bits per word supported on SPI master controller? (spi-dw.c driver supports only 8 and 16 bits)

2. How do we set chip select to active until spi transfer completes 3 byte or 20 bit data.?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The technical reference manual for the A10 SoC HPS says the SPI controller supports data size from 4 to 16 bits. To access a device with 20-bit data you'll probably have to implement a soft SPI controller in the FPGA fabric and access that from the HPS. That would obviously require a custom driver unless you can find a soft SPI core that already has Linux support.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Thanks for your reply,

    There should option to set the chip select pin as force active form SPI master.

    Can you please share information regarding that or register level details of SPI master controller.