Anyone know where2 find max tso and th for sdram

Hi everyone,

Does anyone have experience on finding maximum holding tim and setup time for calculation needed for SDRAM timing??

I am abit confused as to which one to use... there are many in the timing report for th and tsu but, the actual tsu and th I found are quite different to the ones used as example in altera doc " SDRAM controller core with Avalon interface".

I had -0.963 for th but it's -5.6 ns in the example. Is this what I should be getting??

because the phase shift I am using (-3.5ns) is close to that of the example (-3.35) so I should be getting similar result....

The sdram i use is the same as the one used in the example. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif