Honored Contributor
Honored ContributorI've seen similar problems with SDRAM, where the kind of random accesses that 'real' code makes can show up problems that walking one style memory tests don't. However I'd expect SRAM to be much better behaved than SDRAM.
I'm assuming that you run your memory tests without a data cache (otherwise you may not be making any memory accesses at all). In your particular case, I'd say that the first thing you need to be certain of is that this isn't a problem with the exception handling - but it does sound like a hardware problem.
