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Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHi All,
After modifying the SRAM interface to fix the timing bug in NIOS II v1.0, everything seems to be working. Here is a short description of what I had to do to get everything working: - First I changed the ALTCLKLOCK’s to ALTPLL’s. This shouldn’t be a prerequisite but since I am using a Cyclone and not an Apex, FLEX10 or Mercury device I decided to go for the ALTPLLs - Next thing to remember is that the PLD_CLKFB input pin is connected to a buffered output of the PLD_CLKOUT pin. - For the Standard and Full_featured designs it means that the sdram_pll’s inclk0 frequency should be exactly the same as the connector_pll’s e0 output clock frequency. The connector_pll;s inclk0 freqency should be equal to the systems input clock frequency (50MHz in the case of the ALTERA development boards – Cyclone and Stratix when using the default crystal oscillator) - Remember to add a phaseDELAY of -3.5 ns at the sdram_pll e0 output for designs that run on the development kits from ALTERA (I don’t know the delays for other development boards but you should be able to find the delay be following the advice in this thread) - If you are using NIOS II version prior to 1.01 fix the SRAM timing bug if you want to work at clock speeds exceeding 50MHz Anyway that’s about it. Thanks to everybody that helped me get through my PLL nightmare.
