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Altera_Forum
Honored Contributor
Honored ContributorALTPLL Problem
After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_ForumHonored Contributor
Honored ContributorHi everyone,
For some or other reason if you compile something enough it either breaks itself or fixes itself :) I can now run the Processor and SDRAM at 50MHz while still having a 40MHz clock for the VGA VHDL. AND the software works too :) I would love to run the CPU and SDRAM at even higher frequencies (like 80MHz or even 100MHz) but as soon as I try to access the SRAM at frequencies above 50MHz it fails to respond ( I doubt that the 40MHz clock has anything to do with this but you (well I) never know.) . Is this normal? As far as I could gather the SRAM should be able to work at frequencies up to 100MHz as the access time is 10ns. On the cyclone dev board the SRAM modules are IDT71V416 S10PH Z0051P which gives an access time of 10ns – if I understood the datasheet correctly :) I know this question should probably start a new thread but: Is there a reason why the SRAM would stop responding at higher frequencies? The SDRAM seems to work fine at frequencies up to about 100MHz – which would be explained by it being PC100 compatible SDRAM. Any SRAM expert out there?
