ALTPLL Problem

Hi janhendrik,

Thanks for that description of your project. I had not read the JPEG thread; that is quite interesting and some people here in our office have expressed interest in doing such a project should the free time ever present itself.

As far as network speed goes, I guess it depends on how big your photos are and how often you want to refresh them. Even at modest clock speeds and full TCP/IP, I think LWIP will be fine for you at 40 or 50Mhz... we run the example web server at 50Mhz and LWIP isn't terribly fast, but a 150KByte JPEG is downloaded in a couple hundred milliseconds (if I remember correctly). The speed shouldn't be any different for uploading.. it will probably be slightly faster as you're going into an SDRAM buffer instead of fetching a file from flash as we do in the web server, and have less work to do while receiving things via a networking stack than composing packets to send. However, LWIP at that speed will probably be too slow if you want to do any kind of video.

As an alternative to networking, you might consider compactflash (the 1gig cards are quite inexpensive these days) and using a file system (we currently have a new and improved compact flash component, but not a free file system). Micrium, who makes MicroC/OS-II, has a filesystem that (I think) is FAT compatible and bolts on to uCOS... I don't know if they offer any deals to universities or not but it might be worth considering.

back to the pll: I just now read this entire thread; I should have done that in the first place... and now understand your PLL problem. From your last report I think you have it right: connector_pll e0 multiplies by 4/5 to get your desired 40mhz output clock, and then the sdram_pll multiplies by 5/4 (along with the "shift") to get 50Mhz again... you should be able to perform the same operation to get other Nios/SDRAM clock speeds to work; fundamentally I think this is correct... so the next question is why doesn't it work??

You might, as a debug measure, take your Nios system clock and drive it out to one of the header pins on the dev board (the expansion headers should each have one of the pins tied to a high-speed I/O suitable for a clock; check the schematic to see which one is labeled clock and trace that back to the proper FPGA I/O number), then measure this against the SDRAM clock we&#39;re already driving out of the FPGA and see if they&#39;re the same frequency, and in phase (well, phase-shifted just a bit as we&#39;ve already discussed). Hopefully this shouldn&#39;t be too much trouble - just add a pin and re-compile one more time http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif