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Altera_Forum
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21 years ago

ALTPLL Problem

After changing the ALTCLOCKPLL’s in the standard vhdl example design to ALTPLL’s everything still worked fine. But when I changed the ratio on the e0 output of the controller_pll from 1/1 to 4/5 my p...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Hi Everyone,

It seems Jesse is right, and I spoke to soon. When I said that it was working the only evidence was that a program actually managed to run from the SDRAM, but it is not performing as I expected it to.

Since I’m not working with all original code that I wrote myself it took longer to figure out what was wrong and that something is in fact wrong. My project is to try and make a FPGA-based Picture Frame as discussed in the JPEG on NIOS II tread on this forum.

I am using the Lancelot Hardware expansion card and VHDL. (available at www.fpga.nl) The code runs beautifully on the hardware system that is provided but then the CPU runs at 50 MHz alongside the VGA VHDL that requires a 40MHz clock to drive the 800 x 600 x 24bit VGA display circuitry.

The only problem with the original Lancelot design is that it doesn’t have a way to get the images from my PC. I have to upload them to the flash – which I suppose is OK. (Un)fortunately I have a lot of pictures and choosing a few favorites is unfair http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

To solve this problem I decided to add networking support. But that introduced a new problem. The original Lancelot code runs from SRAM and with the added LWIP there is not enough free space to store the images in the SRAM.

So what I want to do is run the new software from SDRAM with all the variables there except for the “frame buffers” that would reside in the SRAM. I would also like to run the CPU (and SDRAM) at speeds above 40MHz to give the LWIP software enough processing power to do a decent job of receiving the images from the network, and then I still want to get JPEG decompression to work http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

This has proven to be more of a challenge than I initially expected when I decided to start working on this project, but it has at least fulfilled its purpose by teaching me a lot about embedded design end development.

If anyone has any suggestions on how I can accommodate the 40MHz restriction without slowing everything else down to a crawl that would be great.

Thanks again for bearing and sharing with me.